ابن الجبل
02-07-2011, 10:45 PM
السلام عليكم ورحمة الله و بركاته
SynaptiCAD Product Suite 16.02a
الشركة:
http://www.syncad.com/syn_ruo.htm
http://img21.imageshack.us/img21/7980/44122731.jpg
حزمة برامج صادرة بتاريخ 2-7-2011تحتوي على:
TestBencher Pro
السعر:
$25,000 دولار
الموقع:
http://www.syncad.com/testbencher_verilog_vhdl_testbench_generator.htm
VeriLogger Extreme
السعر:
$4,000 دولار
VeriLogger Pro
السعر:
$3,000 دولار
BugHunter Pro
السعر:
$5,000 دولار
DataSheet Pro
السعر:
$9,200 دولار
WaveFormer Pro
السعر:
$5,750 دولار
WaveFormer Lite
Timing Diagrammer Pro
السعر:
$3,450 دولار
GigaWave Viewer
السعر:
$2,000 دولار
Vhdl2Verilog
اGates-on-the-Fly
السعر:
$10,000 دولار
VeriLogger Extreme
السعر:
$8,000 دولار
Transaction Tracker
$4,000 دولار
و بذلك يصل سعر الحزمة الى ما يقارب 70.000$ سبعين الف دولار
صممت هذه الحزمة من البرامج على يد مهندسين كهربائيين بهدف محاكاة و تحليل التصاميم و الافكار بدون الحاجة لانهائها ثم معاينتها
بل يتم هذا من خلال هذه الحزمة التي توفر الوقت و الجهد و التي تحتوي على كثير من البرامج و المحاكيات و المترجمات
و لنعرف ما هي هذه الحزمة نختصر تقييما و مراجعة للبروفيسور James K. Peckol, Ph.D
من جامعة واشنطن بالولايات المتحدة الاميركية قسم الهندسة الكهربائية:
Introduction and Overview
The Electrical Engineering Department at the University of Washington offers a rich set of courses for undergraduates and graduates in the field of digital systems and digital design. Such courses range from the study of LSI and VLSI design and digital signal processing to computer network telecommunications, embedded systems (including consumer electronics), and digital and computer systems design. In each area, we have a growing demand for more sophisticated and powerful modeling and simulation tools. During the last year, we have continued to make significant and increasing use of the SynaptiCAD design suite in most of our undergraduate digital classes. To that end, VeriLogger Pro has become the development environment of choice for most of the students. We have been using v9.0 of the sofware for approximately eighteen months now. Our comments will appear below.
The Application of the SynaptiCAD Tool Suite
During the last four years, the SynaptiCAD tool suite has been the Verilog modeling tool in EE 271 and EE 478. We have now moved it into EE 472 as well, but, on a smaller scale. A growing number of the EE 478 students have also made good use of the timing generation capability. All of the classes have access to a very good Unix based Verilog tool and design suite as well. Nonetheless, the SynaptiCAD tool suite has become the first choice for the students in several of the other digital oriented classes identified above.
In EE 271, EE 472, and EE 478, the SynaptiCAD tool suite supports the design, development and test of basic combinational and sequential digital circuits. In EE 271 and EE 478, the application problems are small to moderate and are relatively straightforward. Typically, the combinational problems have a gate complexity of several hundred gate equivalents and a sequential complexity of several dozen flip-flop equivalents. EE472 utilizes the tool suite for designing and implementing simple peripheral devices that can be controlled and operated from the embedded target processor.
As part of the full development process, the students must implement their designs using the GAL16V8 and GAL22V10 Programmable Logic Devices and a handful of TTL and CMOS glue logic chips. Such a requirement means that the students must first design and model their system using the SynaptiCAD tool suite then import the Verilog source into the Lattice ISPDesignExpert tool for synthesis into a JED file that is used to program the PLDs. In our courses, the designs are done at the structural level although some behavioural implementations are appearing in the more advanced courses.
The students' opinion of the tools continues to be very positive and enthusiastic. They were pleased with the modeling power of the tools as well as the suite's interface and the ease with which they could become productive. The inclusion of the project template in the main window when a new project is created is very helpful.
For, EE 476, and EE 477 (VLSI classes), the fact that the SynaptiCAD tools run on a PC rather than Unix has been important. They prefer the PC environment because it is more familiar and also because the user interface to the tools is easier to work with. For these classes, rather that using the complete Unix based development process as described earlier, they are initially designing then debugging their designs on the PC, moving to Unix for synthesis, then back to the PC for checking the synthesized results.
Computing Facilities
The Electrical Engineering department at the University of Washington has several hundred 2-3 GHz machines running Windows XP. Ideally, the SynaptiCAD tools would be served to all of the undergraduate and graduate students in the EE department. The total number of students using the tools would be approximately 400-500.
Summary
We have used the SynaptiCAD package of design tools for four years. The tools have been available to and used to varying degrees by students in EE 271, EE 471, EE 472, EE 476, EE 477, EE 478, and EE 498. All of the classes have access to a very good Unix based Verilog tool and design suite as well.
Their primary application has been to the design of small to modestly complex digital systems implemented using PLDs and to the design and development of moderately complex VLSI systems. In general, the students are comfortable with the tool. They find it easy to learn and to work with and in many cases prefer it to the Unix based alternative. Our experience working with and evaluating the SynaptiCAD 9.0 release has been positive.
فهي تستعمل من الطلاب و المهندسين للتصميم و المحاكاة و التطوير
نعود للحزمة
TestBencher Pro
http://www.syncad.com/art/test_bench_generation_testbencher.gif
برنامج اختباري يوفر الوقت الكثير خصوصا لاختلافات ال HDL و هي hardware description language او Verilog
لتفاصيل اكثر:
http://www.syncad.com/testbencher_verilog_vhdl_testbench_generator.htm
Timing Diagrammer Pro
http://www.syncad.com/art/timing_diagrammer_screen.png
Timing Diagrammer Pro has everything that you expect in a timing diagram editor: a modeless drawing and editing environment; delays, setups, and holds for performing timing analysis; time markers; seven graphical waveform states; virtual and group buses; clocks with formulas; as well as a variety of ways to document your work. A great timing analysis tool at a great price, Timing Diagrammer Pro is a must-have for any engineer.
للتفاصيل:
http://www.syncad.com/timing_diagrammer_timing_diagram_editor.htm
WaveFormer Pro
http://www.syncad.com/art/waveformer_main_in_out.png
WaveFormer Pro is a revolutionary new rapid-prototyping EDA tool that helps you design faster and with fewer mistakes. WaveFormer Pro enables you to automatically determine critical paths, verify timing margins, adjust for reconvergent fanout effects, and perform "what if" analysis to determine optimum clock speed. WaveFormer Pro also lets you specify and analyze system timing and perform Boolean level simulation without the need for schematics or simulation models. When your timing diagram is complete, you can then generate digital stimuli for your favorite Verilog, VHDL, SPICE or gate-level simulator. WaveFormer Pro also has the ability to import and annotate simulation and logic analyzer data, for publication quality design documentation
التفاصيل:
http://www.syncad.com/waveformer_waveform_editor.htm
DataSheet Pro
http://www.syncad.com/art/datasheet_main_screen.png
DataSheet Pro is SynaptiCAD's top of the line timing digaram editor, providing the ultimate environment for documentation professionals working with multi-diagram projects. Datasheet Pro's project management features allow users to efficiently combine diagrams from multiple engineers into one project with uniform formatting. Using Object Linking and Embedding (OLE), users can embed timing diagrams into other publishing programs. These images can be edited at any time directly from the publishing program by double clicking on the image to launch DataSheet Pro with the selected timing diagram. Other features include style sheets, view support, web-ready image generation, analog waveform import and display, and support for the industry-standard Timing Diagram Markup Language (TDML) format. Documentation professionals will be able to receive timing diagrams produced by design engineers using any TDML-compatible product, such as WaveFormer Pro or Timing Diagrammer Pro, and embed them directly into publishing programs like FrameMaker and Word.
للتفاصيل:
http://www.syncad.com/datasheet_pro.htm
VeriLogger Pro
http://www.syncad.com/art/verilogger_design_flow.gif
VeriLogger Pro, by SynaptiCAD is a complete design and verification environment for ASIC and FPGA designers. It contains a new type of Verilog simulation environment that combines all the features of a traditional Verilog simulator with the most powerful graphical test vector generator on the planet. Model testing is so fast in VeriLogger Pro that you can perform true bottom-up testing of every model in your design, a critical step often skipped in the race to market. Test vectors can be imported or exported from HP logic analyzers, pattern generators, and 3rd party VHDL, Verilog, and SPICE simulators for reuse. Simulation features include waveform viewing, optimized gate-level simulation, single-step debugging, point-and-click breakpoints, hierarchical browser for project management, and batch execution
التفاصيل:
http://www.syncad.com/vlog_pro.htm
VeriLogger Extreme
http://www.syncad.com/art/verilog_extreme_design_flow.gif
VeriLogger Extreme is a completely new, high-performance compiled-code Verilog 2001 simulator that significantly reduces simulation debug time. VeriLogger Extreme offers fast simulation of both RTL and gate-level simulations with SDF timing information. VeriLogger Extreme supports design libraries and design flows for all major ASIC and FPGA vendors, including Actel, Altera, Atmel, LSI Logic, QuickLogic, and Xilinx
التفاصيل:
http://www.syncad.com/verilogger_verilog_simulator.htm
BugHunter
http://www.syncad.com/art/bughunter_vhdl_verilog_debugger.gif
BugHunter uses the SynaptiCAD graphical environment and supports all major HDL simulators. It has the ability to launch the simulator, provide single step debugging, unit-level test bench generation, streaming of waveform data, project management, and a hierarchy tree. The unit-level test bench generation is unique in that it lets the user draw stimulus waveforms and then generates the stimulus model and wrapper code and launches the code. It is one of the fastest ways to test a model and make sure that everything is working correctly. The debugger also has exceptional support for VCD waveform files.
With an integrated debugging environment you can graphically build a project, launch a simulation, and view the results in just a few minutes. The interface also manages the test bench interface so that it is easy to create a set of regression tests to run the design through
التفاصيل:
http://www.syncad.com/vhdl_verilog_debugger.htm
Gigawave Viewer
http://www.syncad.com/art/gigawave_simulator_patterngenerator_logicanalyzer_ oscilloscope.gif
Gigawave Viewer combines SynaptiCAD's free VCD WaveViewer with our high-performance gigawave compression engine to create the lowest cost waveform viewer capable of handling multi-gigabyte VCD files. Gigawave viewer also comes with a PLI-based library that can be integrated with your favorite simulator to generate highly compressed BTIM files. Using BTIM waveform dumping can speed up simulation by up to 6x over dumping using an ordinary VCD dump and the resulting files are generally 200x smaller. BTIM files also load much faster than VCD files (typically around 500x faster)! GigaWave also loads SPICE results, TDML, logic analyzer data, and more.
التفاصيل:
http://www.syncad.com/vcd_waveform_viewer.htm
Transaction Tracker
http://www.syncad.com/art/TransTrackWaveEXP.gif
SynaptiCAD's new Transaction Tracker is a PSL/Sugar-based verification tool for viewing simulation data as higher-level transactions, instead of as simple waveforms. Users specify transaction patterns (temporal assertions) to match against using the PSL Sugar language, and Transaction Tracker displays matches and partial matches of these patterns graphically as "transaction records".
This tool also provides a powerful interface for learning the syntax of the PSL language. Several simulators have been released that support PSL assertions, but one of the problems is that users have to learn another language before they become effective with using the tool. With Transaction Tracker, the results are graphical and instantaneous, so users can build up complicated equations by typing in a few terms and seeing the results and then continually adding on until the code matches to the correct transaction pattern.
التفاصيل:
http://www.syncad.com/Trans_Tracker_main.htm
Gates-on-the-Fly
http://www.syncad.com/art/gates_on_the_fly_netlist_analyzer.gif
Gates-on-the-Fly (GOF) graphically analyzes and edits large Verilog netlists that have been generated from a synthesis or layout tool. Netlists sometimes require changes to either meet timing closure specifications, fix functional logic bugs, or to repartition a design. Using GOF, you can easily find and view specific logic cones in your design on a schematic to visualize just the paths you need to see without unnecessary clutter. GOF also simplifies mapping from RTL level constructs to their gate-level equivalents, so that you can pinpoint the locations where changes need to be made. GOF's ECO mode supports both graphical and script-based editing features for tracking ECO changes. Metal-only ECO operations are also supported with an automatic spare gates flow.
التفاصيل:
http://www.syncad.com/gates_on_the_fly_netlist_analyzer_eco_gof.htm
================================================== ==============
تثبيت الحزمة كلها في تثبيت واحد كاي برنامج اخر
ترخيص الحزمة ترخيص دائم و هو ترخيص Site Floating مفتوح و غير محدود
ثبت البرنامج و انسخ ملف الترخيص و هو syncad.lic الى مكان تثبيت البرنامج و الصق فقط
================================================== =============
للتحميل على اكثر من سيرفر
http://www.6ybh-upload.com/z06rn6k6capj/SiCADPS16.02a.READ.NFO-Lz0.rar
http://www.enterupload.com/wwh02s9jiew3/SiCADPS16.02a.READ.NFO-Lz0.rar.html
http://www.filesonic.com/file/1352415444
http://www.fileserve.com/file/yTtB9Yr
http://pyramidfiles.com/n7hu8kzkkefo/SiCADPS16.02a.READ.NFO-Lz0.rar.html
SynaptiCAD Product Suite 16.02a
الشركة:
http://www.syncad.com/syn_ruo.htm
http://img21.imageshack.us/img21/7980/44122731.jpg
حزمة برامج صادرة بتاريخ 2-7-2011تحتوي على:
TestBencher Pro
السعر:
$25,000 دولار
الموقع:
http://www.syncad.com/testbencher_verilog_vhdl_testbench_generator.htm
VeriLogger Extreme
السعر:
$4,000 دولار
VeriLogger Pro
السعر:
$3,000 دولار
BugHunter Pro
السعر:
$5,000 دولار
DataSheet Pro
السعر:
$9,200 دولار
WaveFormer Pro
السعر:
$5,750 دولار
WaveFormer Lite
Timing Diagrammer Pro
السعر:
$3,450 دولار
GigaWave Viewer
السعر:
$2,000 دولار
Vhdl2Verilog
اGates-on-the-Fly
السعر:
$10,000 دولار
VeriLogger Extreme
السعر:
$8,000 دولار
Transaction Tracker
$4,000 دولار
و بذلك يصل سعر الحزمة الى ما يقارب 70.000$ سبعين الف دولار
صممت هذه الحزمة من البرامج على يد مهندسين كهربائيين بهدف محاكاة و تحليل التصاميم و الافكار بدون الحاجة لانهائها ثم معاينتها
بل يتم هذا من خلال هذه الحزمة التي توفر الوقت و الجهد و التي تحتوي على كثير من البرامج و المحاكيات و المترجمات
و لنعرف ما هي هذه الحزمة نختصر تقييما و مراجعة للبروفيسور James K. Peckol, Ph.D
من جامعة واشنطن بالولايات المتحدة الاميركية قسم الهندسة الكهربائية:
Introduction and Overview
The Electrical Engineering Department at the University of Washington offers a rich set of courses for undergraduates and graduates in the field of digital systems and digital design. Such courses range from the study of LSI and VLSI design and digital signal processing to computer network telecommunications, embedded systems (including consumer electronics), and digital and computer systems design. In each area, we have a growing demand for more sophisticated and powerful modeling and simulation tools. During the last year, we have continued to make significant and increasing use of the SynaptiCAD design suite in most of our undergraduate digital classes. To that end, VeriLogger Pro has become the development environment of choice for most of the students. We have been using v9.0 of the sofware for approximately eighteen months now. Our comments will appear below.
The Application of the SynaptiCAD Tool Suite
During the last four years, the SynaptiCAD tool suite has been the Verilog modeling tool in EE 271 and EE 478. We have now moved it into EE 472 as well, but, on a smaller scale. A growing number of the EE 478 students have also made good use of the timing generation capability. All of the classes have access to a very good Unix based Verilog tool and design suite as well. Nonetheless, the SynaptiCAD tool suite has become the first choice for the students in several of the other digital oriented classes identified above.
In EE 271, EE 472, and EE 478, the SynaptiCAD tool suite supports the design, development and test of basic combinational and sequential digital circuits. In EE 271 and EE 478, the application problems are small to moderate and are relatively straightforward. Typically, the combinational problems have a gate complexity of several hundred gate equivalents and a sequential complexity of several dozen flip-flop equivalents. EE472 utilizes the tool suite for designing and implementing simple peripheral devices that can be controlled and operated from the embedded target processor.
As part of the full development process, the students must implement their designs using the GAL16V8 and GAL22V10 Programmable Logic Devices and a handful of TTL and CMOS glue logic chips. Such a requirement means that the students must first design and model their system using the SynaptiCAD tool suite then import the Verilog source into the Lattice ISPDesignExpert tool for synthesis into a JED file that is used to program the PLDs. In our courses, the designs are done at the structural level although some behavioural implementations are appearing in the more advanced courses.
The students' opinion of the tools continues to be very positive and enthusiastic. They were pleased with the modeling power of the tools as well as the suite's interface and the ease with which they could become productive. The inclusion of the project template in the main window when a new project is created is very helpful.
For, EE 476, and EE 477 (VLSI classes), the fact that the SynaptiCAD tools run on a PC rather than Unix has been important. They prefer the PC environment because it is more familiar and also because the user interface to the tools is easier to work with. For these classes, rather that using the complete Unix based development process as described earlier, they are initially designing then debugging their designs on the PC, moving to Unix for synthesis, then back to the PC for checking the synthesized results.
Computing Facilities
The Electrical Engineering department at the University of Washington has several hundred 2-3 GHz machines running Windows XP. Ideally, the SynaptiCAD tools would be served to all of the undergraduate and graduate students in the EE department. The total number of students using the tools would be approximately 400-500.
Summary
We have used the SynaptiCAD package of design tools for four years. The tools have been available to and used to varying degrees by students in EE 271, EE 471, EE 472, EE 476, EE 477, EE 478, and EE 498. All of the classes have access to a very good Unix based Verilog tool and design suite as well.
Their primary application has been to the design of small to modestly complex digital systems implemented using PLDs and to the design and development of moderately complex VLSI systems. In general, the students are comfortable with the tool. They find it easy to learn and to work with and in many cases prefer it to the Unix based alternative. Our experience working with and evaluating the SynaptiCAD 9.0 release has been positive.
فهي تستعمل من الطلاب و المهندسين للتصميم و المحاكاة و التطوير
نعود للحزمة
TestBencher Pro
http://www.syncad.com/art/test_bench_generation_testbencher.gif
برنامج اختباري يوفر الوقت الكثير خصوصا لاختلافات ال HDL و هي hardware description language او Verilog
لتفاصيل اكثر:
http://www.syncad.com/testbencher_verilog_vhdl_testbench_generator.htm
Timing Diagrammer Pro
http://www.syncad.com/art/timing_diagrammer_screen.png
Timing Diagrammer Pro has everything that you expect in a timing diagram editor: a modeless drawing and editing environment; delays, setups, and holds for performing timing analysis; time markers; seven graphical waveform states; virtual and group buses; clocks with formulas; as well as a variety of ways to document your work. A great timing analysis tool at a great price, Timing Diagrammer Pro is a must-have for any engineer.
للتفاصيل:
http://www.syncad.com/timing_diagrammer_timing_diagram_editor.htm
WaveFormer Pro
http://www.syncad.com/art/waveformer_main_in_out.png
WaveFormer Pro is a revolutionary new rapid-prototyping EDA tool that helps you design faster and with fewer mistakes. WaveFormer Pro enables you to automatically determine critical paths, verify timing margins, adjust for reconvergent fanout effects, and perform "what if" analysis to determine optimum clock speed. WaveFormer Pro also lets you specify and analyze system timing and perform Boolean level simulation without the need for schematics or simulation models. When your timing diagram is complete, you can then generate digital stimuli for your favorite Verilog, VHDL, SPICE or gate-level simulator. WaveFormer Pro also has the ability to import and annotate simulation and logic analyzer data, for publication quality design documentation
التفاصيل:
http://www.syncad.com/waveformer_waveform_editor.htm
DataSheet Pro
http://www.syncad.com/art/datasheet_main_screen.png
DataSheet Pro is SynaptiCAD's top of the line timing digaram editor, providing the ultimate environment for documentation professionals working with multi-diagram projects. Datasheet Pro's project management features allow users to efficiently combine diagrams from multiple engineers into one project with uniform formatting. Using Object Linking and Embedding (OLE), users can embed timing diagrams into other publishing programs. These images can be edited at any time directly from the publishing program by double clicking on the image to launch DataSheet Pro with the selected timing diagram. Other features include style sheets, view support, web-ready image generation, analog waveform import and display, and support for the industry-standard Timing Diagram Markup Language (TDML) format. Documentation professionals will be able to receive timing diagrams produced by design engineers using any TDML-compatible product, such as WaveFormer Pro or Timing Diagrammer Pro, and embed them directly into publishing programs like FrameMaker and Word.
للتفاصيل:
http://www.syncad.com/datasheet_pro.htm
VeriLogger Pro
http://www.syncad.com/art/verilogger_design_flow.gif
VeriLogger Pro, by SynaptiCAD is a complete design and verification environment for ASIC and FPGA designers. It contains a new type of Verilog simulation environment that combines all the features of a traditional Verilog simulator with the most powerful graphical test vector generator on the planet. Model testing is so fast in VeriLogger Pro that you can perform true bottom-up testing of every model in your design, a critical step often skipped in the race to market. Test vectors can be imported or exported from HP logic analyzers, pattern generators, and 3rd party VHDL, Verilog, and SPICE simulators for reuse. Simulation features include waveform viewing, optimized gate-level simulation, single-step debugging, point-and-click breakpoints, hierarchical browser for project management, and batch execution
التفاصيل:
http://www.syncad.com/vlog_pro.htm
VeriLogger Extreme
http://www.syncad.com/art/verilog_extreme_design_flow.gif
VeriLogger Extreme is a completely new, high-performance compiled-code Verilog 2001 simulator that significantly reduces simulation debug time. VeriLogger Extreme offers fast simulation of both RTL and gate-level simulations with SDF timing information. VeriLogger Extreme supports design libraries and design flows for all major ASIC and FPGA vendors, including Actel, Altera, Atmel, LSI Logic, QuickLogic, and Xilinx
التفاصيل:
http://www.syncad.com/verilogger_verilog_simulator.htm
BugHunter
http://www.syncad.com/art/bughunter_vhdl_verilog_debugger.gif
BugHunter uses the SynaptiCAD graphical environment and supports all major HDL simulators. It has the ability to launch the simulator, provide single step debugging, unit-level test bench generation, streaming of waveform data, project management, and a hierarchy tree. The unit-level test bench generation is unique in that it lets the user draw stimulus waveforms and then generates the stimulus model and wrapper code and launches the code. It is one of the fastest ways to test a model and make sure that everything is working correctly. The debugger also has exceptional support for VCD waveform files.
With an integrated debugging environment you can graphically build a project, launch a simulation, and view the results in just a few minutes. The interface also manages the test bench interface so that it is easy to create a set of regression tests to run the design through
التفاصيل:
http://www.syncad.com/vhdl_verilog_debugger.htm
Gigawave Viewer
http://www.syncad.com/art/gigawave_simulator_patterngenerator_logicanalyzer_ oscilloscope.gif
Gigawave Viewer combines SynaptiCAD's free VCD WaveViewer with our high-performance gigawave compression engine to create the lowest cost waveform viewer capable of handling multi-gigabyte VCD files. Gigawave viewer also comes with a PLI-based library that can be integrated with your favorite simulator to generate highly compressed BTIM files. Using BTIM waveform dumping can speed up simulation by up to 6x over dumping using an ordinary VCD dump and the resulting files are generally 200x smaller. BTIM files also load much faster than VCD files (typically around 500x faster)! GigaWave also loads SPICE results, TDML, logic analyzer data, and more.
التفاصيل:
http://www.syncad.com/vcd_waveform_viewer.htm
Transaction Tracker
http://www.syncad.com/art/TransTrackWaveEXP.gif
SynaptiCAD's new Transaction Tracker is a PSL/Sugar-based verification tool for viewing simulation data as higher-level transactions, instead of as simple waveforms. Users specify transaction patterns (temporal assertions) to match against using the PSL Sugar language, and Transaction Tracker displays matches and partial matches of these patterns graphically as "transaction records".
This tool also provides a powerful interface for learning the syntax of the PSL language. Several simulators have been released that support PSL assertions, but one of the problems is that users have to learn another language before they become effective with using the tool. With Transaction Tracker, the results are graphical and instantaneous, so users can build up complicated equations by typing in a few terms and seeing the results and then continually adding on until the code matches to the correct transaction pattern.
التفاصيل:
http://www.syncad.com/Trans_Tracker_main.htm
Gates-on-the-Fly
http://www.syncad.com/art/gates_on_the_fly_netlist_analyzer.gif
Gates-on-the-Fly (GOF) graphically analyzes and edits large Verilog netlists that have been generated from a synthesis or layout tool. Netlists sometimes require changes to either meet timing closure specifications, fix functional logic bugs, or to repartition a design. Using GOF, you can easily find and view specific logic cones in your design on a schematic to visualize just the paths you need to see without unnecessary clutter. GOF also simplifies mapping from RTL level constructs to their gate-level equivalents, so that you can pinpoint the locations where changes need to be made. GOF's ECO mode supports both graphical and script-based editing features for tracking ECO changes. Metal-only ECO operations are also supported with an automatic spare gates flow.
التفاصيل:
http://www.syncad.com/gates_on_the_fly_netlist_analyzer_eco_gof.htm
================================================== ==============
تثبيت الحزمة كلها في تثبيت واحد كاي برنامج اخر
ترخيص الحزمة ترخيص دائم و هو ترخيص Site Floating مفتوح و غير محدود
ثبت البرنامج و انسخ ملف الترخيص و هو syncad.lic الى مكان تثبيت البرنامج و الصق فقط
================================================== =============
للتحميل على اكثر من سيرفر
http://www.6ybh-upload.com/z06rn6k6capj/SiCADPS16.02a.READ.NFO-Lz0.rar
http://www.enterupload.com/wwh02s9jiew3/SiCADPS16.02a.READ.NFO-Lz0.rar.html
http://www.filesonic.com/file/1352415444
http://www.fileserve.com/file/yTtB9Yr
http://pyramidfiles.com/n7hu8kzkkefo/SiCADPS16.02a.READ.NFO-Lz0.rar.html